In advanced integrated circuits, multiple levels of interconnect are required to electrically couple various devices together, and to route electrical signals from one area of the integrated circuit to another. In addition, as the device density of an integrated circuit increases, more levels of interconnect are generally required to fabricate it. The parasitic resistance associated with these various levels of interconnect, however, must be minimized because high interconnect resistance degrades the performance and the reliability of an integrated circuit.
In the past, doped regions of silicon and polysilicon have been used as interconnects in integrated circuits. These doped regions, however, have a high resistance, and therefore the performance and the reliability of advanced integrated circuits fabricated with these interconnects is degraded. Accordingly, a need exists for a method for forming low resistance interconnects in advanced integrated circuits.